1/4 rev. b structure silicon monolithic integrated circuit product 7 x 7 matrix led driver for mobile phone type BH6948GU figure 1. highly effective charge pump circuit t hat can be switched 1 time, 1.5 times, and 2 times pressure automatically. (190ma / max) 2. 7-channel led driver that can contorol pwm (iomax = 31ma/ch, current step = 1ma) 3. 7-channel pmos-sw controlled with 1/8tdma 4. it is possible to make 49(7x7) le d shine by pmos-sw and the led driver 5. spi interface 6. wafer level csp pacage for space constrained applications 62pin (4.1mm 4.1 mm height = 1.0mm-max) absolute maximum ratings (ta = 25 ) parameter symbol rating unit maximum supply voltage v max 5.5 v power dissipation pd 1.47 w operating temperature range t opr -30 +85 storage temperature range t stg -55 +125 when using more than at ta=25 , it is reduced 14.7mw per 1 . when rhom specification board 50mm x 58mm mounting. cautions : a device may be destroyed when it is used on the conditions beyond this value. moreover, the usual operat ion is not guaranteed. operating conditions parameter symbol range unit block vbat1 voltage 1 v bat1 3.15 4.5 v vref/bgr vbatcp voltage 1 v batcp v dcdc dvdd1 voltage 2 v dvdd1 1.7 3.1 v i/o dvdd2 voltage 2 v dvdd2 2.7 3.1 v logic 1 49led lighting 2 dvdd1 Q dvdd2 this product is not especially designed to be protected from radioactivity. status of this document. the japanese version of this document is the formal specificati on. a customer may use this translation version only for reference to help reading the formal version. if there are any differences in translation version of this doc ument, formal version takes priority.
2/4 rev. b electrical characteristics (unless otherwise specified, ta=25 ,vbat1=vbatcp=vbatcp1-3=3.6v,dvdd1=1.8v,dvdd2=2.85v) parameter symbol spec units condition min typ max circuit current stand-by circuit current i st - 0 8.8 ua stand-by mode (rstb=?h?) dc-dc converter current1 i qcp1 - 0.93 1.4 ma 1times mode dc-dc converter current2 i qcp2 - 6.4 9.6 ma 1.5tim es mode (cpout=4.75v) dc-dc converter current3 i qcp3 - 4.8 7.2 ma 2times mode (cpout=4.75v) dcdc converter cpout voltage1 v cp1 4.55 4.75 4.95 v 1.5times mode no load cpout output current1 i cp1 - - 190 ma 1.5times mode, vcpout>4v 49 led lighting cpout voltage2 v cp2 4.55 4.75 4.95 v 2.0times mode no load cpout output current2 i cp2 - - 190 ma 2.0times mode, vcpout>4v 49 led lighting cpout voltage3 v cp3 5.1 5.3 5.5 v 1. 5times mode no load cpout output current3 i cp3 - - 190 ma 1.5times mode, vcpout>4v 49 led lighting cpout voltage4 v cp4 5.1 5.3 5.5 v 2. 0times mode no load cpout output current4 i cp4 - - 190 ma 2.0times mode, vcpout>4v 49 led lighting oscillator frequency fosc 0.96 1.20 1.44 mhz pmos switch leak current when off (sw1 7 total) i leakp - - 7.0 a when 35h(matrixcnt)bit0(start)=0 current driver (lo-mode, led1~7) output current1 i o -8.5 - +8.5 % i=1ma setting output current2 3 i o2 -8.0 - +8.0 % i=2 3ma setting output current4 31 i o4 -7.0 - +7.0 % i=4 31ma setting output current matching1 mat1 - - 11.5 % i=1 3ma setting, mat1=(iomax-iomin)/iominx100 output current matching2 mat2 - - 10 % i=4 31ma setting mat2=(iomax-iomin)/iominx100 leak current when off (sw1 7 total) i leak - - 7.0 ua when 35h(matrixcnt)bit0(start)=0 current driver (rgb with pwm led1~7) pwm on duty1 pwmd1 1.54 5.04 8.54 % pwm1 7set=5digit pwm on duty2 pwmd2 43.7 47.2 40.7 % pwm1 7set=32digit pwm on duty3 pwmd3 84.6 88.1 91.6 % pwm1 7set=58digit under voltage lockout uvlo threshold v uvlo 2.0 2.25 2.6 v vbat falling uvlo hysteresis v uvlo 50 100 150 mv soft-start ss mode time t ss 1.6 2.0 2.4 ms short circuit protector scp threshold v scp 1.0 1.2 1.4 v cpout falling delay time t dly 8 10 12 ms reset time t rst 80 100 120 ms over current protector ocp threshold i ocp - 790 - ma over voltage protector ovp threshold vovp 5.50 5.62 5.74 v led dropout detector detect voltage v dr 0.36 0.40 0.44 v spi i/f input ?h? level v ih 1.4 - dvdd1 +0.3 v input ?l? level v il -0.3 - 0.4 v ?h? level input current i ih - 0 1 ua ?l? level input current i ih - 0 1 ua rstb input ?h? level v ih 1.4 - dvdd1 +0.3 v input ?l? level v il -0.3 - 0.4 v ?h? level input current i ih - 0 1 ua ?l? level input current i il - 0 1 ua
3/4 rev. b block diagram terminal list package outline fbga62r1 ball name fbga62r1 ball no. function test1 a1 test terminal 1 ( please be sure connect to gnd) cpoutsw a2 power supply for sw1 7 sw3 a3 p-mos sw3 output sw1 a4 p-mos sw1 output sw7 a5 p-mos sw7 output led1 a6 led1 driver output gndle2 a7 gnd for led1 3 test2 a8 test terminal 2 ( please be sure connect to gnd) sw5 b1 p-mos sw5 output sw4 b2 p-mos sw4 output cpoutsw b3 power supply for sw1 7 sw2 b4 p-mos sw2 output led7 b5 led7 driver output led6 b6 led6 driver output led2 b7 led2 driver output led3 b8 led3 driver output gnda c1 gnd for vref, iref sw6 c2 p-mos sw6 output iref c4 led constant current driver current setting terminal test3 c5 test terminal 3 ( please be sure connect to gnd) gndle3 c6 gnd for led4 7 led5 c7 led5 driver output led4 c8 led4 driver output vref d1 stabilization power supply for iref, vsatdet, osc vbat1 d2 power supply for bgr, vref, scp vref12 d3 standard for osc, vsatdet, iref rstb d4 reset terminal gnd d5 gnd terminal clk d6 4 line serial interface clk di d7 4 line serial interfac datain dgnd d8 gnd for internal logic dver e1 device version vbatcp2 e2 power supply for charge pump gnd e3 gnd terminal gnd e4 gnd terminal ce e5 4 line serial interface ce do e6 4 line serial interface dataout dvdd1 e7 power supply for interface dvdd2 e8 power supply for internal logic vbatcp f1 power supply for charge pump section vbatcp3 f2 power supply for charge pump section test4 f3 test terminal 4 ( please be sure connect to gnd) testo f4 test output terminal ( please should be left open when used) gnd f6 gnd terminal gnd f7 gnd terminal vbatcp f8 power supply for charge pump section cpin1 g1 power supply for charge pump section step-up voltage circuit test5 g2 test terminal 5 ( please be sure to connect to vbat) cpout2 g3 charge pump section constant voltage output gnd g4 gnd terminal gnd g5 gnd terminal gnd g6 gnd terminal gnd g7 gnd terminal gndcp g8 gnd for charge pump section gnd h1 gnd terminal c2p h2 charge pump section flying capacitor2 on side of plus cpout1 h3 charge pump section constant voltage output c1p h4 charge pump section flying capacitor1 on side of plus c2m h5 charge pump section flying capacitor2 on side of minus cpin2 h6 power supply for charge pump section step-up voltage circuit c1m h7 charge pump section flying capacitor1 on side of minus gnd h8 gnd terminal bh6948 lot no. iref osc vbat1 dvdd2 sw4 sw3 sw2 sw7 sw 6 sw5 led5 led4 led2 sw1 led7 led6 led1 rstb ce clk di do cpout 1 led3 test1 bgr / vref gnd cpout 2 iref vref12 vref dgnd gndle 2 gndle3 vbat logic tdma cpoutsw tdma tdma tdma tdma tdma tdma tdma pwm 31ma /ch 1ma step dvdd1 gndcp vbatcp vbat c2m c1m c2p c1p cpin1 cpin2 charge pump x1, x1.5, x2 dver test0 vbatcp1 vbatcp2 vbatcp3 cpoutsw1 vbat tdma pwm slope spi/if t00 t01 t02 t03 t04 t05 t06 test2 test3 test4 test5 gnda g8 h2 h5 f8 d2 f1 e2 f2 g1 h6 h7 h4 a1 a8 c5 f3 g2 f4 b2 b1 c2 a5 b3 a2 g3 h3 b7 b8 c8 c7 b6 b5 a7 a4 b4 a3 c6 a6 e1 d8 e6 d7 d6 e5 d4 e7 c1 c4 d1 d3 e8 d5,e3,e4, f6,f7,g4, g5,g6,g7, h1,h8
4/4 rev. b use-related cautions (1) absolute maximum ratings if applied voltage (v max ), operating temperature range (topr), or other absolu te maximum ratings are exceeded, there is a risk of damage. since it is not possible to identify short, open, or ot her damage modes, if special m odes in which absolute maximum ratings are exceeded are assumed, consider appl ying fuses or other physical safety measures. (2) power supply lines in the design of the board pattern, make power supply and gnd line wi ring low impedance. when doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and analog power s upply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns. similarly take pattern design into acc ount for gnd lines as well. when there is a small signal gnd and a la rge current gnd, it is recommended that y ou separate the large current gnd pattern and small signal gnd pattern and provide si ngle point grounding at the reference point of the set so that voltage variation due to resistance components of the pa ttern wiring and large currents do not cause the sm all signal gnd voltage to change. take care that the gnd wiring pattern of externally attached components also does not change. furthermore, for all power supply pins of the lsi, in conjunction with inserting capacitors between power supply and gnd pins, when using electrolytic capa citors, determine constants upon adequately confirming that cap acitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (3) gnd voltage make the potential of a gnd pin such that it will be the lowest potential even if oper ating below that. in addition, confirm t hat there are no pins for which the potential becomes less than a gnd by actually including transition phenomena. (4) shorts between pins and misinstallation when installing in the set board, pay adequate attention to orie ntation and placement discrepancies of the lsi. if it is instal led erroneously, there is a risk of lsi damage. there also is a risk of damage if it is shorted by a foreign substance getting bet ween pins or between a pin an d a power supply or gnd. (5) operation in strong magnetic fields be careful when using the lsi in a strong ma gnetic field, since it may malfunction. (6) input pins parasitic elements inevitably are formed on an lsi structure due to potential relationships. because parasitic elements operat e, they give rise to interference with circui t operation and may be the cause of malfuncti ons as well as damage. accordingly, tak e care not to apply a lower voltage than gnd to an input pin or use the lsi in other ways such that parasitic elements operate. moreover, do not apply a voltage to an input pin when the power supply voltage is not being applie d to the lsi. furthermore, when the power supply voltage is being appl ied, make each input pin a voltage less than the power supply voltage as well as wit hin the guaranteed values of electrical characteristics. (7) externally attached capacitors when using ceramic capacitors for external ly attached capacitors, dete rmine constants upon taking into account a lowering of th e rated capacitance due to dc bias and capacitance change due to factors such as temperature. (8) thermal shutdown circuit (tsd) when the junction temperature becomes higher, the thermal shutdown circuit operates and turns the switch off. the thermal shutdown circuit, which is aimed at isola ting the lsi from thermal runaway as much as possible, is not aimed at the protection or guarantee of the lsi. therefore, do not continuously use the lsi with this circui t operating or use the lsi assuming its opera tion. (9) thermal design perform thermal design in which there are adequate margins by taking into account the permissible dissipation (pd) in actual states of use. 10t est terminal and unused terminal processing please process a test terminal and unused te rminal according to explana tions of the function manual and the application note, e tc. to be unquestionable while real used. moreover, please inquire of the person in charge of our company about the terminal withou t the explanation especially. 11 rush current for ics with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. therefore, give specia l consideration to power coupl ing capacitance, power wring, width of gnd wiring, and routing of wiring.
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